View M25P32-VME6G_4375113.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M25P32
32-Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface
Features

32 Mbit of Flash memory 2.7 V to 3.6 V single supply voltage SPI bus compatible serial interface 75 MHz clock rate (maximum) VPP = 9 V for Fast Program/Erase mode (optional) Page Program (up to 256 bytes) - in 0.64 ms (typical) Sector Erase (512 Kbit) in 0.6 s (typical) Bulk Erase: - in 23 s (typical) - in 17 s (typical with VPP = 9 V) Deep Power-down mode 1 A (typical) Electronic Signatures - JEDEC standard two-byte signature (2016h) - Unique ID code (UID) +16 bytes of CFI data - RES instruction, one-byte, signature (15h), for backward compatibility Hardware Write Protection of the memory area selected using the BP0, BP1 and BP2 bits More than 100 000 Erase/Program cycles per sector More than 20 year data retention Packages - ECOPACK(R) (RoHS compliant) SO8W (MW) 208 mils VDFPN8 (ME) 8 x 6 mm (MLP8)

VFQFPN8 (MP) 6 x 5 mm
SO16 (MF) 300 mils width

December 2007
Rev 11
1/53
www.numonyx.com 1
Contents
M25P32
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . 10 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 Fast Program/Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 6.2 6.3 6.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/53
M25P32 6.4.2 6.4.3 6.4.4
Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 29 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Release from Deep Power-down and Read Electronic Signature (RES) . 35
7 8 9 10 11 12 13
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3/53
List of tables
M25P32
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC characteristics (T9HX technology) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 x 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SO16 wide - 16-lead Plastic Small Outline, 300 mils body width, mechanical data. . . . . . 47 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SO8W 8 lead Plastic Small Outline, 208 mils body width, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4/53
M25P32
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 23 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 25 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 28 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 36 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 44 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 x 6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SO16 wide - 16-lead Plastic Small Outline, 300 mils body width, package outline . . . . . . 47 VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SO8W 8 lead Plastic Small Outline, 208 mils body width, package outline . . . . . . . . . . . . 49
5/53
Description
M25P32
1
Description
The M25P32 is a 32 Mbit (4M x 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. An enhanced Fast Program/Erase mode is available to speed up operations in factory environment. The device enters this mode whenever the VPPH voltage is applied to the Write Protect/Enhanced Program Supply Voltage pin (W/VPP). The memory is organized as 64 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 16384 pages, or 4,194,304 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers the M25P32 in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant.
6/53
M25P32 Figure 1. Logic diagram
VCC
Description
D C S W/VPP HOLD M25P32
Q
VSS
AI07483b
Table 1.
Signal names
Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply voltage Ground Input Input Output Input Input Input Input Direction
Signal name C D Q S W/VPP HOLD VCC VSS
Figure 2.
VDFPN connections
M25P32 S Q W/VPP VSS 1 2 3 4 8 7 6 5 VCC HOLD C D
AI08518b
1. There is an exposed central pad on the underside of the MLP8 package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/53
Description Figure 3. SO connections
M25P32 HOLD VCC DU DU DU DU S Q 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C D DU DU DU DU VSS W/VPP
AI07484c
M25P32
1. DU = Don't Use 2. See Package mechanical section for package dimensions, and how to identify pin-1.
8/53
M25P32
Signal description
2
2.1
Signal description
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
9/53
Signal description
M25P32
2.6
Write Protect/Enhanced Program supply voltage (W/VPP)
W/VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). If VPP is in the range of VPPH it acts as an additional power supply pin. In this case VPP must be stable until the Program/Erase algorithm is completed.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
10/53
M25P32
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
Bus Master and memory devices on the SPI bus
VSS VCC R SDO
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1)
SDI SCK CQD VCC VSS R SPI Memory Device R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
SPI Bus Master
CS3
CS2 CS1 S W HOLD S W HOLD S W HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure that the M25P32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k assuming that the time constant R*Cp (Cp = parasitic , capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance.
11/53
SPI modes
M25P32 Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 5.
CPOL CPHA C
SPI modes supported
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
12/53
M25P32
Operating features
4
4.1
Operating features
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP)).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
4.4
Fast Program/Erase mode
The Fast Program/Erase mode is used to speed up programming/erasing. The device enters the Fast Program/Erase mode during the Page Program, Sector Erase or Bulk Erase instruction whenever a voltage equal to VPPH is applied to the W/VPP pin. The use of the Fast Program/Erase mode requires specific operating conditions in addition to the normal ones (VCC must be within the normal operating range):

the voltage applied to the W/VPP pin must be equal to VPPH (see Table 10) ambient temperature, TA must be 25 C 10 C, the cumulated time during which W/VPP is at VPPH should be less than 80 hours
4.5
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
13/53
Operating features
M25P32
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed. While in the Deep Power-down mode, the device ignores all Write, Program and Erase instructions (see Deep Power-down (DP)) This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
4.7
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P32 features the following data protection mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W/VPP) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection, as all Write, Program and Erase instructions are ignored.
14/53
M25P32 Table 2. Protected area sizes
Memory content
Operating features
Status Register content BP2 BP1 BP0 bit bit bit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 none Upper 64th (Sector 63) Protected area
Unprotected area All sectors(1) (64 sectors: 0 to 63) Lower 63/64ths (63 sectors: 0 to 62)
Upper 32nd (two sectors: 62 and 63) Lower 31/32nds (62 sectors: 0 to 61) Upper sixteenth (four sectors: 60 to 63) Lower 15/16ths (60 sectors: 0 to 59)
Upper eighth (eight sectors: 56 to 63) Lower seven-eighths (56 sectors: 0 to 55) Upper quarter (sixteen sectors: 48 to Lower three-quarters (48 sectors: 0 to 47) 63) Upper half (thirty-two sectors: 32 to 63) All sectors (64 sectors: 0 to 63) Lower half (32 sectors: 0 to 31) none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
4.8
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 6). During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition.
15/53
Operating features Figure 6. Hold condition activation
M25P32
C
HOLD
Hold Condition (standard use)
Hold Condition (non-standard use)
AI02029D
16/53
M25P32
Memory organization
5
Memory organization
The memory is organized as:

4,194,304 bytes (8 bits each) 64 sectors (512 Kbits, 65536 bytes each) 16384 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7.
HOLD W/VPP S C D Q Control Logic
Block diagram
High Voltage Generator
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
3FFFFFh
Y Decoder
Size of the read-only memory area
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI08519b
17/53
Memory organization Table 3. Memory organization
Sector 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3F0000h 3E0000h 3D0000h 3C0000h 3B0000h 3A0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2F0000h 2E0000h 2D0000h 2C0000h 2B0000h 2A0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1F0000h 1E0000h 1D0000h Address range 3FFFFFh 3EFFFFh 3DFFFFh 3CFFFFh 3BFFFFh 3AFFFFh 39FFFFh 38FFFFh 37FFFFh 36FFFFh 35FFFFh 34FFFFh 33FFFFh 32FFFFh 31FFFFh 30FFFFh 2FFFFFh 2EFFFFh 2DFFFFh 2CFFFFh 2BFFFFh 2AFFFFh 29FFFFh 28FFFFh 27FFFFh 26FFFFh 25FFFFh 24FFFFh 23FFFFh 22FFFFh 21FFFFh 20FFFFh 1FFFFFh 1EFFFFh 1DFFFFh
M25P32
18/53
M25P32 Table 3. Memory organization (continued)
Sector 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h Address range
Memory organization
1CFFFFh 1BFFFFh 1AFFFFh 19FFFFh 18FFFFh 17FFFFh 16FFFFh 15FFFFh 14FFFFh 13FFFFh 12FFFFh 11FFFFh 10FFFFh 0FFFFFh 0EFFFFh 0DFFFFh 0CFFFFh 0BFFFFh 0AFFFFh 09FFFFh 08FFFFh 07FFFFh 06FFFFh 05FFFFh 04FFFFh 03FFFFh 02FFFFh 01FFFFh 00FFFFh
19/53
Instructions
M25P32
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
20/53
M25P32 Table 4.
Instruction WREN WRDI RDID RDSR WRSR READ FAST_READ PP SE BE DP
Instructions Instruction set
Description Write Enable Write Disable Read Identification Read Status Register Write Status Register Read Data bytes Read Data bytes at higher speed Page Program Sector Erase Bulk Erase Deep Power-down Release from Deep Powerdown, and Read Electronic Signature Release from Deep Powerdown One-byte instruction Address Dummy code bytes bytes 0000 0110 0000 0100 1001 1111 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 06h 04h 9Fh 05h 01h 03h 0Bh 02h D8h C7h B9h 0 0 0 0 0 3 3 3 3 0 0 0 1010 1011 ABh 0 0 0 0 0 0 0 0 0 1 0 0 0 0 3 Data bytes 0 0 1 to 20 1 to 1 1 to 1 to 1 to 256 0 0 0 1 to
RES
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 8. Write Enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
21/53
Instructions
M25P32
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
Figure 9.
S 0 C Instruction D High Impedance Q
AI03750D
1
2
3
4
5
6
7
22/53
M25P32
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:

Manufacturer identification (one byte) Device identification (two bytes) A Unique ID code (UID) followed by 16 bytes of CFI data
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (16h). The UID is set to 10h and indicates that 16 bytes, related to the CFI content, are following. Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit Unique ID code followed by 16 bytes of CFI content will be shifted out on Serial Data Output (Q). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read Identification (RDID) data-out sequence
Device identification Manufacturer identification Memory type 20h 20h Memory capacity 16h 10h 16 bytes UID CFI content
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S 0 C Instruction D Manufacturer Identification High Impedance Q MSB 15 14 13 MSB 3 2 1 0 MSB
AI06809c
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification
UID + CFI Data
23/53
Instructions
M25P32
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 11. Table 6.
b7 SRWD 0 0 BP2 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.
24/53
M25P32
Instructions
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
25/53
Instructions
M25P32
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 12. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Figure 12. Write Status Register (WRSR) instruction sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
26/53
M25P32 Table 7. Protection modes
Mode Write Protection of the Status Register
Instructions
W/VPP SRWD signal bit 1 0 0 0
Memory content Protected area(1) Unprotected area(1)
1
1
Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is Hardware Hardware write protected Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summarized in Table 7. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/VPP):
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W/VPP) High. If Write Protect (W/VPP) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
27/53
Instructions
M25P32
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
1. Address bits A23 to A22 are Don't Care.
28/53
M25P32
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
1. Address bits A23 to A22 are Don't Care.
29/53
Instructions
M25P32
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
30/53
M25P32 Figure 15. Page Program (PP) instruction sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S
2072
2073
2074
2075
2076
2077
2
2078
1
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3
Data Byte 256
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
0
MSB
MSB
AI04082B
1. Address bits A23 to A22 are Don't Care.
2079
31/53
Instructions
M25P32
6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data Input (D). Any address inside the Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. Figure 16. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
1. Address bits A23 to A22 are Don't Care.
32/53
M25P32
Instructions
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 17. Bulk Erase (BE) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
33/53
Instructions
M25P32
6.11
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 13). To take the device out of Deep Power-down mode, the Release from Deep Power-down and Read Electronic Signature (RES) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (Q). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Deep Power-down (DP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
AI03753D
34/53
M25P32
Instructions
6.12
Release from Deep Power-down and Read Electronic Signature (RES)
To take the device out of Deep Power-down mode, the Release from Deep Power-down and Read Electronic Signature (RES) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the old-style 8-bit Electronic Signature, whose value for the M25P32 is 15h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for reasons of backward compatibility, only, and should not be used for new designs. New designs should, instead, make use of the JEDEC 16-bit Electronic Signature, and the Read Identifier (RDID) instruction. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the old-style 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge of Serial Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 19. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic Signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 13. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
35/53
Instructions Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence
M25P32
S 0 C Instruction 3 Dummy Bytes tRES2 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
D High Impedance Q
23 22 21 MSB
3
2
1
0 Electronic Signature Out 7 MSB Deep Power-down Mode Stand-by Mode
AI04047C
6
5
4
3
2
1
0
1. The value of the 8-bit Electronic Signature, for the M25P32, is 15h.
Figure 20. Release from Deep Power-down (RES) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRES1
High Impedance Q Deep Power-down Mode Stand-by Mode
AI04078B
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 20), still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 13. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
36/53
M25P32
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level
These values are specified in Table 8. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state:

The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
37/53
Power-up and Power-down Figure 21. Power-up timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed
M25P32
Device fully accessible
time
AI04009C
Table 8.
Symbol tVSL(1) tPUW(1) VWI(1)
Power-up timing and VWI threshold
Parameter VCC(min) to S low Time delay to Write instruction Write Inhibit voltage Min. 30 1 1.5 10 2.5 Max. Unit s ms V
1. These parameters are characterized only.
38/53
M25P32
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9.
Symbol TSTG TLEAD VIO VCC VPP VESD Storage temperature Lead temperature during soldering Input and output voltage (with respect to Ground) Supply voltage Fast Program/Erase voltage Electrostatic Discharge Voltage (Human Body model)
(2)
Absolute maximum ratings
Parameter Min. -65 Max. 150 see (1) -0.6 -0.6 -0.2 -2000 VCC + 0.6 4.0 10.0 2000 Unit C C V V V V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 , R2 = 500 ).
39/53
DC and AC parameters
M25P32
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10.
Symbol VCC VPPH TA TAVPP Supply voltage Supply voltage on W/VPP pin for Fast Program/Erase mode Ambient operating temperature Ambient operating temperature for fast Program/Erase mode
Operating conditions
Parameter Min. 2.7 8.5 -40 15 25 Typ. Max. 3.6 9.5 85 35 Unit V V C C
Table 11.
Symbol CL
AC measurement conditions
Parameter Load capacitance Input rise and fall times Input pulse voltages Input timing reference voltages Output timing reference voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max. Unit pF ns V V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 22. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC
AI07455
0.2VCC
Table 12.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA=25 C and a frequency of 20 MHz.
40/53
M25P32 Table 13.
Symbol ILI ILO ICC1 ICC2
DC and AC parameters DC characteristics
Parameter Input leakage current Output leakage current Standby current Deep Power-down current S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 75 MHz, Q = open ICC3 Operating current (READ) C = 0.1VCC / 0.9.VCC at 33 MHz, Q = open Operating current (PP) Operating current (WRSR) Operating current (SE) Operating current (BE) Operating current for Fast Program/Erase mode VPP operating current in Fast Program/Erase mode Input low voltage Input high voltage Output low voltage Output high voltage IOL = 1.6 mA IOH = -100 A VCC-0.2 S = VCC S = VCC S = VCC S = VCC S = VCC, VPP = VPPH S = VCC, VPP = VPPH - 0.5 0.7VCC 4 15 15 15 15 20 20 0.3VCC VCC+0.4 0.4 mA mA mA mA mA mA mA V V V V Test condition (in addition to those in Table 10) Min. Max. 2 2 50 10 12 Unit A A A A mA
ICC4 ICC5 ICC6 ICC7 ICCPP IPP VIL VIH VOL VOH
41/53
DC and AC parameters Table 14. AC characteristics (T9HX technology)
Applies only to products made with T9HX technology, identified with Process digit "4"(1) Test conditions specified in Table 10 and Table 11 Symbol Alt. Parameter Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR Clock frequency for READ instructions tCLH Clock High time tCLL Clock Low time Clock rise time(5) (peak to peak) Clock fall time(5) (peak to peak) Min. Typ.(2)
M25P32
Max.
Unit
fC fR tCH(3) tCL(2) tCLCH(4) tCHCL
(4)
fC
D.C. D.C. 9 9 0.1 0.1 5 5 2 5 5 5 100
75 33
MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ
(4)
tCSS S active setup time (relative to C) S not active hold time (relative to C) tDSU Data In setup time tDH Data In hold time S active hold time (relative to C) S not active setup time (relative to C) tCSH S deselect time tDIS tV tHO Output Disable time Clock Low to Output valid Output hold time HOLD setup time (relative to C) HOLD hold time (relative to C) HOLD setup time (relative to C) HOLD hold time (relative to C) tLZ tHZ HOLD to Output Low-Z HOLD to Output High-Z Write Protect setup time Write Protect hold time Enhanced Program supply voltage High to Chip Select Low S High to Deep Power-down mode S High to Standby mode without Electronic Signature Read S High to Standby mode with Electronic Signature Read
8 8 0 5 5 5 5 8 8 20 100 200 3 30 30
ns ns ns ns ns ns ns ns ns ns ns ns s s s
tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(4) tHLQZ(4) tWHSL(6) tSHWL
(6)
tVPPHSL(7) tDP(4) tRES1(4) tRES2(4)
42/53
M25P32 Table 14. AC characteristics (T9HX technology) (continued)
DC and AC parameters
Applies only to products made with T9HX technology, identified with Process digit "4"(1) Test conditions specified in Table 10 and Table 11 Symbol tW Alt. Parameter Write Status Register cycle time Page Program cycle time (256 bytes) tPP (8) Page Program cycle time (n bytes) Page Program cycle time (VPP = VPPH) (256 bytes) Sector Erase cycle time tSE Sector Erase cycle time (VPP = VPPH) Bulk Erase cycle time tBE Bulk Erase cycle time (VPP = VPPH) Min. Typ.(2) 1.3 0.64 int(n/8) x 0.02(9) 0.64 0.6 3 0.6 23 80 13 s s 5 ms Max. 15 Unit ms
1. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 12: Part numbering. 2. Typical values given for TA = 25 C. 3. tCH + tCL must be greater than or equal to 1/ fC 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. 8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 9. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
Figure 23. Serial input timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
43/53
DC and AC parameters Figure 24. Write Protect Setup and Hold timing during WRSR when SRWD=1
M25P32
W/VPP tWHSL
tSHWL
S
C
D High Impedance Q
AI07439b
Figure 25. Hold timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
44/53
M25P32 Figure 26. Output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
DC and AC parameters
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
Figure 27. VPPH timing
End of PP, SE or BE (identified by WPI polling)
S
C
D
PP, SE, BE
VPPH W/VPP
tVPPHSL ai12092
45/53
Package mechanical
M25P32
11
Package mechanical
Figure 28. VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 x 6 mm, package outline
D
E
E2
e
b A L ddd A1
VDFPN-02
D2 K L1
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 15.
VDFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 8 x 6 mm, package mechanical data
millimeters inches Max 1.00 0.00 0.40 8.00 5.16 0.05 6.00 4.80 1.27 - 0.82 0.50 0.45 0.60 0.15 8 8 0.0197 - 0.2362 0.1890 0.0500 - 0.0323 0.0177 0.0236 0.0059 - 0.35 0.05 0.48 0.0157 0.3150 0.2031 0.0020 Typ 0.0335 0.0000 0.0138 Min Max 0.0394 0.0020 0.0189
Symbol Typ A A1 b D D2 ddd E E2 e K L L1 N 0.85 Min
46/53
M25P32
Package mechanical Figure 29. SO16 wide - 16-lead Plastic Small Outline, 300 mils body width, package outline
D
16 9
h x 45
C E H
1
8
A2 A ddd A1 L
B SO-H
e
1. Drawing is not to scale.
Table 16.
SO16 wide - 16-lead Plastic Small Outline, 300 mils body width, mechanical data
millimeters inches Max. 2.65 0.30 0.51 0.32 10.50 7.60 - 10.65 0.75 1.27 8 0.10 0.050 Typ. Min. 0.093 0.004 0.013 0.009 0.398 0.291 - 0.394 0.010 0.016 0 Max. 0.104 0.012 0.020 0.013 0.413 0.299 - 0.419 0.030 0.050 8 0.004
Symbol Typ. A A1 B C D E e H h L ddd 1.27 Min. 2.35 0.10 0.33 0.23 10.10 7.40 - 10.00 0.25 0.40 0
47/53
Package mechanical
M25P32
Figure 30. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package outline
D D1
E E1
E2
e
b A2 L D2
A
A1 A3
VFQFPN-01
1. Drawing is not to scale.
Table 17.
VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data
millimeters inches Max 1.00 0.05 0.0256 0.0079 0.35 0.48 0.0157 0.2362 0.2264 3.20 3.60 0.1339 0.1969 0.1870 3.80 - 0.50 4.30 - 0.75 12 0.1575 0.0500 0.0236 0.1496 - 0.0197 0.1693 - 0.0295 12 0.1260 0.1417 0.0138 0.0189 Typ 0.0335 Min 0.0315 0.0000 Max 0.0394 0.0020
Symbol Typ A A1 A2 A3 b D D1 D2 E E1 E2 e L 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.60 0.85 Min 0.80 0.00
48/53
M25P32
Package mechanical Figure 31. SO8W 8 lead Plastic Small Outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 18.
SO8W 8 lead Plastic Small Outline, 208 mils body width, package mechanical data
millimeters inches Max 2.50 0.00 1.51 0.40 0.20 0.35 0.10 0.25 2.00 0.51 0.35 0.10 6.05 5.02 7.62 1.27 - 0 0.50 8 6.22 8.89 - 10 0.80 0.050 0.198 0.300 - 0 0.020 8 0.016 0.008 0.000 0.059 0.014 0.004 Typ Min Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 - 10 0.031
Symbol Typ A A1 A2 b c CP D E E1 e k L N Min
49/53
Part numbering
M25P32
12
Part numbering
Table 19.
Example:
Ordering information scheme
M25P32 - V MW 6 T P
Device Type M25P = Serial Flash Memory for Code Storage
Device Function 32 = 32 Mbit (4M x 8)
Operating Voltage V = VCC = 2.7 to 3.6 V
Package MF = SO16 (300 mils width) ME = VDFPN8 8 x 6 mm (MLP8) MW = SO8W (208 mils width)(1) MP = VFQFPN 6 x 5 mm (MLP8)(1)
Device Grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow
Option blank = Standard Packing T = Tape and Reel Packing
Plating Technology P or G = ECOPACK(R) (RoHS compliant)
1. Packages available only in products processed in the T9HX technology.
Note:
For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 m, process digit "4"), please contact your nearest Numonyx Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
50/53
M25P32
Revision history
13
Revision history
Table 20.
Date 28-Apr-2003 15-May-2003 20-Jun-2003 18-Jul-2003 24-Sep-2003
Document revision history
Revision 0.1 0.2 0.3 0.4 0.5 Changes Target Specification Document written in brief form Target Specification Document written in full 8x6 MLP8 and SO16(300 mil) packages added tPP, tSE and tBE revised SO16 package code changed. Output Timing Reference Voltage changed. Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. Change of naming for VDFPN8 package. Document promoted to Product Preview Document promoted to Preliminary Data. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified Device grade information further clarified Document promoted to mature datasheet. Footnotes removed from P and G options in Ordering Information table. Minor wording improvements made. Read Identification (RDID), Deep Power-down (DP) and Release from Deep Power-down and Read Electronic Signature (RES) instructions, and Active Power, Standby Power and Deep Power-down modes paragraph clarified. Updated Page Program (PP) instructions in Page Programming, Page Program (PP) and Table 14: AC characteristics. Fast Program/Erase mode added and Power-up specified for Fast Program/Erase mode in Power-up and Power-down section. W pin changed to W/VPP. (see Write Protect/Enhanced Program supply voltage (W/VPP) description). tVPPHSL added to Table 14: AC characteristics and tPP for Fast Program/Erase mode added. Figure 27: VPPH timing inserted. Note 2 added below Figure 28 All packages are ECOPACK(R) compliant. Blank option removed under Plating Technology in Table 19 VDFPN8 package specifications updated (see Section 11: Package mechanical). MLP8 5 x 6 mm and SO8W packages added (see Section 11: Package mechanical). VCC supply voltage and VSS ground descriptions added. Figure 4: Bus Master and memory devices on the SPI bus updated and explanation added below. Table 9: Absolute maximum ratings: VIO max modified and TLEAD added. Products in T9HX technology introduced (see Table 14: AC characteristics (T9HX technology)). Small text changes.
04-Dec-2003
0.6
10-Dec-2003 01-Apr-2004 05-Aug-2004 01-Oct-2004
1.0 2.0 3.0 4.0
01-Apr-2005
5.0
01-Aug-2005
6.0
23-Jan-2006
7.0
10-Feb-2006
8.0
28-Nov-2006
9
51/53
Revision history Table 20.
Date
M25P32 Document revision history
Revision Changes Section 7: Power-up and Power-down modified. Read Identification instruction modified in Section 6.3: Read Identification (RDID). Inserted UID and CFI content columns in Table 5: Read Identification (RDID) data-out sequence. Modified Data bytes for RDID instruction in Table 4: Instruction set. Modified Q signal in Figure 10: Read Identification (RDID) instruction sequence and data-out sequence. Modified Test condition and maximum value for ICC3 in Table 13: DC characteristics. Modified the maximum value for fC in Table 14: AC characteristics (T9HX technology). Table 14: AC characteristics removed. Applied Numonyx branding.
15-Jun-2007
10
10-Dec-2007
11
52/53
M25P32
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved.
53/53

▲Up To Search▲

Price & Availability of M25P32-VME6G

	To Download M25P32-VME6G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .